As CMOS technology continues to scale further into the sub-micron region, the width of active regions between adjacent gates structures of metal oxide semiconductor (MOS) transistors and the width of the active regions between the gate structures and field regions is constantly being reduced. Unfortunately, as the widths reduce, the resistances of these regions rise due to the regions being narrower. The increased resistance is becoming a major limitation of the MOS transistor performance.
In tune with the reduction in the width of active regions between adjacent gates structures of metal oxide semiconductor (MOS) transistors and the width of the active regions between the gate structures and field regions, the scaling of CMOS technology also desires that the width of the sidewall structures located along the sidewalls of the gate structures be reduced. The width of the sidewall structures, however, determines how far from the edge of the gate structures the deep source/drain regions are located. Nevertheless, due to the diffusion of dopants, the thermal annealing process designed to activate the dopants in the polysilicon gate and the deep source/drain regions of the MOS transistors typically pushes the edge of the deep source/drain regions towards each other and towards the edge of the transistor gate structure. If the deep source/drain regions get too close to each other, undesirable enhanced leakage may result when the transistor is in its off state. Reducing the width of the sidewall structures is therefore typically limited by the thermal diffusion process that takes place during the annealing that occurs after the formation of the deep source/drain regions.
As CMOS technology continues to scale there is therefore an increasing need for a method to reduce the width of the sidewall spacers without causing the source/drain regions to be positioned in such a location as to negatively affect the MOS transistor.